The present invention relates to a semiconductor device fabrication technique, more specifically a semiconductor device including DRAM-type memory device, and a method for fabricating the same.
A DRAM is a semiconductor device which can be formed of one transistor and one capacitor. Various structures and fabrication methods have been conventionally studied for semiconductor devices of higher density and higher integration. Especially for a structure of a capacitor of a DRAM, which much influences higher integration, it is significant how to ensure a required storage capacitance without preventing higher integration of the device.
For higher integration, it is essential to reduce a memory cell area and to reduce also an area where a capacitor is to be formed. Then, it has been proposed that a column-shaped or a cylindrical capacitor structure is used so that the capacitor can have a surface area which is increased in the direction of the height, whereby a required storage capacitance can be ensured without increasing an area occupied by a region where the capacitor is formed.
A method for fabricating a conventional semiconductor device having a cylindrical capacitor structure will be explained with reference to FIGS. 41A-41C, 42A-42B, and 43A-43B. A method for fabricating a conventional semiconductor device having a column-shaped capacitor structure has the same basic fabrication process.
First, in the same way as in the method for fabricating a usual MOS transistor, a memory cell transistor including a gate electrode 102 and source/drain diffused layers 104, 106, and a peripheral circuit transistor including a gate electrode 108 and a source/drain diffused layer 110 are formed on a silicon substrate 100.
Next, a bit line 114 electrically connected respectively to the source/drain diffused layer 104 through a plug 112 and an interconnection layer 116 electrically connected to the source/drain diffused layer 110 through a plug 115 are formed on an inter-layer insulation film 118 covering the memory cell transistor and the peripheral circuit transistor. In the figure, the bit line 114 is indicated by the dotted line because the bit line 114 does not appear in the shown section.
Then, an inter-layer insulation film 120 is formed on the inter-layer insulation film 118 having the bit line 114 and the interconnection layer 116 formed thereon (FIG. 41A).
Next, a plug 124 electrically connected to the source/drain diffused layer 106 through a plug 122 is buried in the inter-layer insulation films 120, 118 (FIG. 41B).
Then, on the inter-layer insulation film 120 with the plug 124 buried in, an etching stopper film 126 of, e.g., a silicon nitride film, an inter-layer insulation film 128 of, e.g., a silicon oxide film, an etching stopper film 130 of, e.g., a silicon nitride film, an inter-layer insulation film 132 of, e.g., a silicon oxide film, and a hard mask 134 of, e.g., an amorphous silicon film are sequentially formed by, e.g., CVD method.
Then, the hard mask 134, the inter-layer insulation film 132, the etching stopper film 130, the inter-layer insulation film 128 and the etching stopper film 126 are patterned by the lithography and etching to form an opening 136 down to the plug 124 (FIG. 41C).
Then, a storage electrode 138 connected to the plug 124 is formed along the inside wall and the bottom of the opening 136 (FIG. 42A).
Next, with the etching stopper film 130 as a stopper, the inter-layer insulation film 132 is isotropically etched to expose the outside surface of the storage electrode 138 (FIG. 42B). The etching stopper film 130 and the inter-layer insulation film 128 function as a support for preventing the storage electrode 138 from falling down or peeling off in the steps following the etching step.
Then, a dielectric film of, e.g., Ta2O5 film or BST film is formed on the entire surface by, e.g., CVD method to form a capacitor dielectric film 140 of the dielectric film, covering the storage electrode 138.
Next, a conducting film is deposited on the entire surface by, e.g., CVD method and patterned to form a plate electrode 142 of the conducting film, covering the storage electrode 138 interposing the capacitor dielectric film 140 therebetween (FIG. 43A).
Thus, a capacitor including the storage electrode 138, the capacitor dielectric film 140 and the plate electrode 142 and connected electrically to the source/drain diffused layer 106 of a memory cell transistor is formed.
Then, a silicon oxide film is deposited on the entire surface by, e.g., CVD method, and the surface of the silicon oxide film is planarized to form an inter-layer insulation film 144 of the silicon oxide film.
Next, a contact hole 146 is formed by the lithography and etching through the inter-layer insulation film 144, the etching stopper film 130, the inter-layer insulation film 128, the etching stopper film 126 and the inter-layer insulation film 120.
Then, a plug 148 connected to the interconnection layer 116 is formed in the contact hole 146 (FIG. 43B).
Next, an interconnection layer (not shown) connected to the plug 148, etc. are formed.
Thus, a DRAM comprising memory cells each having one transistor and one capacitor is fabricated.
As described above, in the conventional method for fabricating the conventional semiconductor device, the etching stopper film 130 and the inter-layer insulation film 128 are provided to thereby prevent the storage electrode 138 from falling down or peeling off in the process, and the semiconductor device including the cylindrical capacitor can be fabricated.
On the other hand, a method which prevents the storage electrode 138 from peeling off without the use of the support has been proposed. Another conventional method for fabricating a semiconductor device, which uses no support for a storage electrode 138 will be explained with reference to FIGS. 44A-44B, 45A-45B, and 46A-46B.
First, in the same way as in the semiconductor device fabrication method shown in FIG. 41A, a memory cell transistor, a peripheral circuit transistor, a bit line 114, an interconnection layer 116, inter-layer insulation films 118, 120, etc. are formed on a silicon substrate 100 (FIG. 44A).
Then, an etching stopper film 126 of, e.g, a silicon nitride film is formed on the inter-layer insulation film 120 by, e.g., CVD method.
Next, the etching stopper film 126 is patterned by the lithography and etching to be removed in a region where a contact hole for connecting the plug 122 to a storage electrode 138 to be formed later is to be formed.
Next, an inter-layer insulation film 132 of, e.g., a silicon oxide film, and a hard mask 134 of, e.g., an amorphous silicon film are formed on the patterned etching stopper film 126 by, e.g., CVD method in the stated order.
Then, the hard mask 134 is patterned by the lithography and etching to remove the hard mask 134 in the region where the storage electrode 138 is to be formed (FIG. 44B).
Next, with the hard mask 134 as a mask and with the etching stopper film 126 as a stopper, the inter-layer insulation films 132, 120, 118 are anisotropically etched to form an opening 136 down to the plug 122 through the inter-layer insulation film 132, the etching stopper film 126, the inter-layer insulation films 120, 118 (FIG. 45A).
Then, the storage electrode 138 connected to the plug 122 is formed along the inside wall and bottom of the opening 136 (FIG. 45B).
Then, with the etching stopper film 126 as a stopper, the inter-layer insulation film 132 is isotropically etched to expose the outside surface of the storage electrode 138 (FIG. 46A).
The storage electrode 138 also functions as a plug for connection to the plug 122, and is formed, buried in the inter-layer insulation films 118, 120, whereby the storage electrode 138 is prevented from falling down or peeling off in the steps following the etching step. Accordingly, it is not necessary that the support is provided by the etching stopper film 130, the inter-layer insulation film 128, etc. as in the above-described semiconductor device fabrication method.
Then, in the same way as in the above-described semiconductor device fabrication method, a capacitor dielectric film 140, a plate electrode 142, an inter-layer insulation film 144, a plug 148, etc. are formed (FIG. 46B).
Thus, a DRAM comprising memory cells each having one transistor and one capacitor is fabricated.
As described above, in the method for fabricating said another conventional semiconductor device, the storage electrode is formed integral with the plug, which makes it unnecessary to additionally provide the support for the storage electrode. A thickness of the insulation film through which the plug 148 is passed can be smaller by a thickness of the etching stopper film 130 and the inter-layer insulation film 128. Accordingly, the steps of forming the insulation film can be omitted, and it is easy to open the contact hole 146 and bury a plug material forming the plug 148. The fabrication process can be accordingly simplified, and the fabrication cost can be low.
However, in using the above-described method for fabricating the semiconductor device shown in FIGS. 41A-41C, 42A-42B, and 43A-43B, it is necessary as described above to add the steps of forming the support for the storage electrode 138, and the contact hole 146 for the plug 148 to be buried in is deep, which increases the fabrication cost and makes its processing itself difficult.
In using the cylindrical storage electrode 138, because the plug 124 contacts an outside atmosphere through the thin storage electrode 138, the upper surface of the plug 124 is often oxidized through the storage electrode 138 when the substrate is exposed to the oxidizing atmosphere in the step of forming the capacitor dielectric film 140, which deteriorates contact characteristics between the storage electrode 138 and the plug 124.
In using the above-described conventional semiconductor device fabrication method shown in FIGS. 44A-44B, 45A-45B, and 46A-46B, the above-described problem of the semiconductor device shown in FIGS. 41A-41C, 42A-42B, and 43A-43B can be solved. However, disalignment in patterning the etching stopper film 126 or the hard mask 134 often causes defective contact of the storage electrode 138 to the plug 122 and breakage of the lower structure due to etching.
The storage electrode 138 is formed in the opening 136 formed with the hard mask as a mask, and as shown in FIG. 47, the pattern of the opening 136 is a flat shape extended in the direction of extension of the bit line 114. This makes the alignment difficult especially in the direction of extension of a word line (a gate electrode 102) in patterning the etching stopper film 126 and the hard mask 134.
When disalignment takes place in the direction of extension of the word line in patterning the hard mask 134 to overlap, as shown in FIG. 48, the opening pattern of the etching stopper film 126 over an edge of the opening pattern of the hard mask 134, the opening 136 is formed in the inter-layer insulation films 120, 118 in a width which is smaller than the pattern formed in the etching stopper film 126, because one of two sides of the opening 136 formed in the inter-layer insulation films 120, 118, which are extended in the direction of extension of the word line is defined by the etching stopper film 126 and the other of the two sides is defined by the hard mask 134. As a result, the micro-loading effect makes the etching difficult, and a contact area between the storage electrode 138 and the plug 122 is decreased. In a worst case, the storage electrode 138 and the plug 122 cannot contact each other (FIG. 49A). Especially in performing the etching in self-alignment with the bit line, the micro-loading effect is more influential because the opening 136 is tapered downward, contouring the etching stopper film formed on the side wall of the bit line.
These phenomena are true with the case that the patterning of the etching stopper film 126 is in the direction of extension of the word line.
When the contact has been successfully opened, but the inter-layer insulation film 132 is etched after the formation of the storage electrode 138, because the region where the etching stopper film 126 is absent is present below the inter-layer insulation film 132, the inter-layer insulation films 120, 118, etc. are etched concurrently with the etching of the inter-layer insulation film 132, which damages the below structure (FIG. 49B).
A semiconductor device structure and a method for fabricating the same which can prevent the storage electrode from falling down or peeling off without the presence of the support for the storage electrode, and which are free from the defective contact and the breakage of the lower structure by disalignment in forming the opening 136 have been expected in consideration of the above-described problems.
It is an object of the present invention to provide a semiconductor device and a method for fabricating the semiconductor device which can prevent the storage electrode from falling down or peeling off without the presence of the support for the storage electrode, and are free from the defective contact and the breakage of the lower structure by disalignment.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a first insulation film formed on a substrate, the first insulation film having a contact hole down to the substrate; a first electrode including a contact part formed in the contact hole, and a projection part connected to only a part of the upper surface of the contact part and projected above the first insulation film, the contact part and the projection part being formed of the same conducting layer; a dielectric film formed on the first electrode; and a second electrode formed on the dielectric film and opposed to the first electrode.
According to another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming on a substrate a first insulation film having a contact hole formed therein; forming a dummy plug in the contact hole; forming a second insulation film on the first insulation film with the dummy plug buried in; forming in the second insulation film an opening for exposing at least a part of the dummy plug; selectively removing the dummy plug through the opening; and forming in the contact hole and the opening a first electrode electrically connected to the substrate.
According to further another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming on a substrate a first insulation film having a contact hole formed therein; forming on the first insulation film a second insulation film, leaving a void in the contact hole; forming in the second insulation film an opening down to the void; and forming in the contact hole and the opening a first electrode, electrically connected to the substrate.
According to further another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming on a substrate a first insulation film having a contact hole formed therein; forming a dummy plug in the contact hole; forming a second insulation film on the first insulation film with the dummy plug buried in; forming in the second insulation film an opening for exposing at least a part of the dummy plug; selectively removing the dummy plug through the opening; and forming in the contact hole and the opening a conducting film, electrically connected to the substrate.
According to further another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming on a substrate a first insulation film having a contact hole formed therein; forming on the first insulation film a second insulation film, leaving a void in the contact hole; forming in the second insulation film an opening down to the void; and forming in the contact hole and the opening a conducting film, electrically connected to the substrate.
A xe2x80x9csubstratexe2x80x9d used in the specification of the present application means not only a semiconductor substrate itself, such as a silicon substrate, but also a semiconductor substrate with transistors, an interconnection layer, insulation films, etc. formed on.
A xe2x80x9cconducting filmxe2x80x9d includes not only electrodes, such as storage electrodes, but also interconnection layers, such as buried interconnections, etc.
As described above, according to the present invention, the dummy plug is formed in the lower inter-layer insulation film, the dummy plug is removed after the opening to be used in forming the storage electrode in the upper inter-layer insulation film has been formed, and the storage electrode is formed partially buried in the contact hole from which the dummy plug has been removed. Accordingly, without an extra support for supporting the storage electrode, the storage electrode is prevented form falling down or peeling off, and defective contact and breakage of the lower structure due to disalignment can be precluded.